Parity check bits have been inserted to data rows of a digital signal at a transmission side for monitoring the circuit quality in a digital wireless communication device. Thus, parity errors have heretofore been detected at a receiving side based on the parity check bits. This type of circuit quality monitoring will be described with reference to FIGS. 1 and 2.
FIGS. 1 and 2 are block diagrams showing an example of a circuit quality monitoring configuration having an error correction function. FIG. 1 shows a transmitting unit, and FIG. 2 shows a receiving unit. The transmitting unit has a parity operation circuit 101, a multiplexer circuit 102, an error correction encoder circuit 103, and a modulation circuit 104. The receiving unit has a demodulation circuit 201, an error correction decoder circuit 202, a separation circuit 203, a parity operation circuit 204, a parity comparison circuit 205, and a circuit alarm initiation circuit 206.
Operation of this circuit quality monitoring configuration will be described. The parity operation circuit 101 in the transmitting unit performs a parity operation on transmission data D in accordance with an algorithm such as even parity or odd parity before parity multiplexing. The multiplexer circuit 102 multiplexes the parity operation results on the transmission data D and outputs the multiplexed data as a transmission signal. The error correction encoder circuit 103 receives from the multiplexer circuit 102 the transmission signal in which the parity has been multiplexed and encodes it. The modulation circuit 104 performs quadrature modulation on the encoded transmission signal and transmits the transmission signal through a wireless transmission line to the counterpart receiving unit.
In the receiving unit, the error correction decoder circuit 202 decodes a received signal demodulated by the demodulation circuit 201. The separation circuit 203 separates the parity operation results, which have been multiplexed in the transmitting unit, from the decoded series of data subjected to error correction. The parity operation circuit 204 performs a parity operation on the series of data subjected to the error correction in accordance with the same algorithm as that used in the transmitting unit. The parity comparison circuit 205 compares the parity operation results which have been obtained from the parity operation circuit 204 with the parity operation results in the transmitting unit which have been separated by the separation circuit 203. The parity comparison circuit 205 generates a parity error pulse (PUPE) when the result of the comparison shows disparity. The circuit alarm initiation circuit 206 counts the number of the parity error pulses and initiates a circuit alarm (AL) when the count of the errors within a predetermined alarm initiation interval exceeds an alarm initiation threshold (THM). Furthermore, after the circuit alarm has been initiated, the circuit alarm initiation circuit 206 releases the circuit alarm (AL) when the count of parity errors within a predetermined alarm release interval is less than an alarm release threshold (THR).
In this conventional example, when an initiation point of an circuit alarm is to be determined, the initiation threshold and the release threshold used as parameters are set based on the relationship between an occurrence frequency of parity errors and a bit error rate (BER). Therefore, the initiation point depends upon the occurrence probability of parity errors.
Some public documents relating to the present invention are listed as follows:                Patent Document 1: Japanese laid-open patent publication No. 2004-320377        Patent Document 2: Japanese laid-open patent publication No. 2006-217101        Patent Document 3: Japanese laid-open patent publication No. 60-144040        Patent Document 4: Japanese laid-open patent publication No. 63-292851        Patent Document 5: Japanese laid-open patent publication No. 05-236030        Patent Document 6: Japanese laid-open patent publication No. 10-145340        